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Ordering number : ENN7053
CMOS IC
LC75412E, 75412W
Electronic Volume Controller for Car Audio Systems
Overview
The LC75412E and 75412W are electronic volume controllers that enable control of volume, balance, fader, bass/treble, loudness, input switching, and input gain using only a small number of external components.
Features
* On-chip buffer amplifier cuts down number of external components * Low switching noise generated by on-chip switch through use of silicon gate CMOS process, for low switching noise when there is no signal * Low switching noise when there is a signal due to use of on-chip zero-cross switching circuit * On-chip 1/2 VDD reference voltage circuit * Controls performed with serial input (CCB)
Functions
* Volume: 0 dB to -79 dB in 1-dB steps, and - (81 positions) Balance function with separate L/R control * Fader: rear output or front output can be attenuated across 16 positions (in 1-dB steps from 0 dB to -2 dB, 2-dB steps from -2 dB to -20 dB, 10-dB steps from -20 dB to -30 dB, and -45 dB, -60 dB, -) * Bass/treble: Each band can be controlled in 2-dB steps from 0 dB to 18 dB. * Input gain: 0 dB to +18.75 dB (1.25-dB steps) amplification is possible for the input signal. * Input switching: Six input signals can be selected for Left and for Right (five are singleended inputs and one is a differential input.) * Loudness: A tap is output from the -32 dB position of a volume control resistor ladder. A loudness function can be implemented by connecting an external RC circuit.
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
O1901RM (OT) No. 7053-1/21
LC75412E, 75412W
Package Dimensions
unit: mm 3159-QIP64E
[LC75412E]
17.2 1.0 1.6 1.0 0.8 14.0 0.35 1.6 1.0 0.15
unit: mm 3190-SQFP64
[LC75412W]
12.0 10.0 0.18
1.25
0.5
1.25
33 48 49 32
0.15
48 49
1.25
33 32
17.2
12.0
0.8
14.0
10.0 0.5
17
1.0 3.0max
64 1 16
15.6
0.8
0.5
0.1 0.5
0.1 2.7
1
16
SANYO: QIP64E
Pin Assignment
LTOUT LSELO
LF1C1
LF1C2
LF1C3
LF3C1
LF3C2
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
LF3C3
LVRIN
LCT
NC
NC
NC
NC
NC
NC
L5P 49 L5M 50 L4 51 L3 52 L2 53 L1 54 L6 55 VDD 56 Vref 57 R6 58 R1 59 R2 60 R3 61 R4 62 R5M 63 R5P 64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 LFIN 31 LFOUT 30 LROUT 29 LAVSS 28 TEST 27 DVSS 26 CL
LC75412E/W
25 DI 24 CE 23 MUTE 22 RAVSS 21 NC 20 TIM 19 RROUT 18 RFOUT 17 RFIN
RTOUT
RF3C1
RF3C2
RSELO
RF1C1
RF1C2
RF1C3
RF3C3
RVRIN
NC
NC
NC
NC
RCT
NC
NC
1.7max
64
1.25
17
SANYO: SQFP64
No. 7053-2/21
1k 0.33F
10k 1000pF 0.001F 0.001F 0.1F 0.1F 1F LSELO 10F LVRIN LF1C1 LF1C2 LF1C3 LF3C1 LF3C2 LF3C3 NC NC NC NC NC NC LTOUT LCT 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 48
+ 32 LVref 31 30 29 28 LVref
L5P
49
LFIN LFOUT LROUT LAVSS TEST 10F 10F PA PA
+ +
L5M
50 LVref LVref
+
L4
51
+
L3
52
1F x 7
+
L2
53
+
L1 Multiplexer ZEROCROSS DET LVref + RVref CONTROL CIRCUIT LOGIC CIRCUIT
54
27 DVSS 26 CCB INTERFACE 25 CL DI 24 CE 23 MUTE 47k 22 NO SIGNAL TIMER 1M RAVSS 21 NC 20 RVref 19 RVref 18 TIM RROUT RFOUT 17 RFIN 10F PA 10F 0.033F CL DI CE COM
+
L6
55
VDD
56
22F
+
Vref
57
+ Multiplexer RVref
R6
58 ZEROCROSS DET
+
R1
59
Equivalent Circuit Block Diagram/Sample Application Circuit
LC75412E, 75412W
+ RVref
R2
60
+
R3
61 +
1F x 7
+
R4
62
PA
+
R5M
63
+
R5P
64
1 NC RCT RVRIN 1k 10k RSELO 1F 1000pF
2
3
4
5 NC
6 NC 0.1F
7 RF1C1
8 RF1C2
9 RF1C3 0.1F
10 NC
11 NC
12 NC
13 RF3C1 0.001F
14 RF3C2
15 RF3C3 0.001F
16 RTOUT
10F
0.33F
No. 7053-3/21
LC75412E, 75412W
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Maximum input voltage Allowable power dissipation Operating temperature Storage temperature Symbol VDD max VIN max Pd max Topr Tstg VDD All input pins Ta 85C, when mounted on board QIP64E SQFP64 Conditions Ratings 11 VSS - 0.3 to VDD + 0.3 680 800 -40 to +85 -50 to +125 Unit V V mW C C
Allowable Operating Ranges at Ta = 25C, VSS = 0 V
Parameter Supply voltage Input high-level voltage Input low-level voltage Input amplitude voltage Input pulse width Setup time Hold time Operating frequency Symbol VDD VIH VIL VIN ToW Tsetup Thold fopg CL CL, DI, CE CL, DI, CE CL VDD CL, DI, CE CL, DI, CE Conditions Ratings min 6.0 4.0 VSS VSS 1 1 1 500 typ max 10 10 1.0 VDD Unit V V V Vp-p s s s kHz
Electrical Characteristics at Ta = 25C, VDD = 9 V, VSS = 0 V
Parameter [Input block] Input resistance Minimum input gain Maximum input gain Step setting error L/R balance [Volume Block] Input resistance Step setting error L/R balance [Tone block] Step setting error Bass control range Treble control range L/R balance ATerr Gbass Gtre BAL max. boost/cut max. boost/cut 15 15 18 18 1.0 21 21 0.5 dB dB dB dB Rvr ATerr BAL LVRIN, RVRIN, loudness off 25 50 100 0.5 0.5 k dB dB Rin Ginmin Ginmax ATerr BAL L1 to L4, L6, R1 to R4, R6 L1 to L4, L6, R1 to R4, R6 25 -1 +16.5 50 0 +18.75 100 +1 +21 0.5 0.5 k dB dB dB dB Symbol Pin Name Conditions Ratings min typ max Unit
Continued on next page.
No. 7053-4/21
LC75412E, 75412W
Continued from preceding page.
Parameter [Fader Block] Input resistance Rfed LFIN, RFIN 0dB to -2dB Step setting error ATerr -2dB to -20dB -20dB to -30dB -30dB to -60dB L/R balance [General] Total harmonic distortion Input crosstalk L/R crosstalk Maximum attenuated output THD (1) THD (2) CT CT VIN = 0dBV, f = 1 kHz VIN = -10dBV, f = 10 kHz VIN = 1Vrms, f = 1 kHz VIN = 1Vrms, f = 1 kHz 80 80 80 90 0.004 0.006 88 88 88 95 5 7 55 CL, DI, CE, VIN = 9 V CL, DI, CE, VIN = 0 V THD = 1%, RL = 10 k flat overall, fIN = 1 kHz VIN = 0 dB, f = 1 kHz -10 2.3 2.5 70 10 15 60 10 0.01 0.01 % % dB dB dB dB V V mA A A Vrms dB BAL 25 50 100 0.5 1 2 3 0.5 k dB dB dB dB dB Symbol Pin Name Conditions Ratings min typ max Unit
Vomin (1) VIN = 1Vrms, f = 1 kHz VIN = 1Vrms, f = 1 kHz Vomin (2) INMUTE, fader - VN (1) VN (2) IDD IIH IIL VCL CMRR Flat overall, IHF-A filter Flat overall, 20 to 20 kHzBPF
Output noise voltage Current drain Input high-level current Input low-level current Maximum input voltage Common-mode rejection ratio
Control Timing and Data Format To control the LC75412E and LC75412W input specified serial data to the CE, CL, and DI pins. The data configuration consists of a total of 52 bits broken down into 8 address bits and 44 data bits.
CE DI CL
B0 B1 B2 B3 A0 A1 A2 A3 D0 D1 D2 D3 D4 D5 D38 D39 D40 D41 D42 D43
CE
1s min
1s 1s 1s min min min
1s min
CL
DI
1s min TDEST
No. 7053-5/21
LC75412E, 75412W Address code (B0 to A3) The LC75412E and 75412W use 8-bit address code and can be used in common with ICs that support SANYO's CCB serial bus. Address Code
(LSB) B0 1 B1 0 B2 0 B3 0 A0 0 A1 0 A2 0 A3 1 (81HEX)
Control code allocation Input Switching Control
D0 0 1 0 1 0 1 D1 0 0 1 1 0 0 D2 0 0 0 0 1 1 Setting L1 (R1) L2 (R2) L3 (R3) L4 (R4) L5 (R5) L6 (R6) Setting
D3
Bit for IC testing: Normally set to 0
Input Gain Control
D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0dB +1.25dB +2.50dB +3.75dB +5.00dB +6.25dB +7.50dB +8.75dB +10.0dB +11.25dB +12.5dB +13.75dB +15.0dB +16.25dB +17.5dB +18.75dB Operation
No. 7053-6/21
LC75412E, 75412W Volume Control (0 to -40dB)
D8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D10 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D11 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 D12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 D13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 D14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -15dB -16dB -17dB -18dB -19dB -20dB -21dB -22dB -23dB -24dB -25dB -26dB -27dB -28dB -29dB -30dB -31dB -32dB -33dB -34dB -35dB -36dB -37dB -38dB -39dB -40dB Operation
No. 7053-7/21
LC75412E, 75412W Volume Control (-41 to -dB)
D8 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D9 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 D10 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 D11 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 D12 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D13 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Operation -41dB -42dB -43dB -44dB -45dB -46dB -47dB -48dB -49dB -50dB -51dB -52dB -53dB -54dB -55dB -56dB -57dB -58dB -59dB -60dB -61dB -62dB -63dB -64dB -65dB -66dB -67dB -68dB -69dB -70dB -71dB -72dB -73dB -74dB -75dB -76dB -77dB -78dB -79dB -
No. 7053-8/21
LC75412E, 75412W Tone Control
D16 D24 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D20 0 D17 D25 1 1 0 1 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 D21 0 D18 D26 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 0 D22 0 D19 D27 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 D23 0 Set to 0 D40 D41 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Bass Treble +18dB +16dB +14dB +12dB +10dB +8dB +6dB +4dB +2dB 0dB -2dB -4dB -6dB -8dB -10dB -12dB -14dB -16dB -18dB
Fader Volume Control
D28 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D29 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D30 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D31 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0dB -1dB -2dB -4dB -6dB -8dB -10dB -12dB -14dB -16dB -18dB -20dB -30dB -45dB -60dB - Operation
Channel Selection Control
D32 0 1 0 1 D33 0 0 1 1 RCH LCH L/R simultaneously Operation
No. 7053-9/21
LC75412E, 75412W Fader Rear/Front Control
D34 0 1 Setting Rear Front
Loudness Control
D35 0 1 Setting OFF ON
Zero-Cross Control
D36 0 1 D37 0 1 Setting Data write through zero-cross detection Zero-cross detection stopped (data write at falling edge of CE)
Zero-Cross Signal Detection Block Control
D38 0 1 0 1 D39 0 0 1 1 Selector Volume Tone Fader Setting
Test Mode Control
D42 0 D43 0 Setting For IC testing. Always set to 0.
No. 7053-10/21
LC75412E, 75412W Pin Functions
Pin Name L1 L2 L3 L4 L6 R1 R2 R3 R4 R6 Pin No. 54 53 52 51 55 59 60 61 62 58 * Single-end input pins Function Equivalent circuit
VDD
LVref RVref
VDD
L5M L5P R5M R5P 50 49 63 64 * Differential input pins
M
-
VDD P
+
LVref RVref VDD
LSEL0 RSEL0
48 1
* Input selector output pins
VDD
LCT RCT 46 3 * Loudness pins. Connect high-pass compensation RC between LCT (RCT) and LVRIN (RVRIN), and connect low-pass compensation RC between LCT (RCT) and GND.
VDD
LVRIN RVRIN 47 2
* Volume and equalizer input pins.
Continued on next page.
No. 7053-11/21
LC75412E, 75412W
Continued from preceding page.
Pin Name Pin No. Function Equivalent circuit
VDD
LF1C1 LF1C2 LF1C3 RF1C1 RF1C2 RF1C3 42 41 40 7 8 9 * Equalizer F1 band filter configuration capacitor connection pins. Connect capacitor between LF1C1 (RF1C1) and LF1C2 (RF1C2) LF1C2 (RF1C2) and LF1C3 (RF1C3)
+ -
VDD FnC1 FnC3
* Equalizer F3 band filter configuration capacitor connection pins. Connect capacitor between LF3C1 (RF3C1) and LF3C2 (RF3C2) LF3C2 (RF3C2) and LF3C3 (RF3C3)
VDD
LF3C1 LF3C2 LF3C3 RF3C1 RF3C2 RF3C3
36 35 34 13 14 15
FnC2
VDD
NC NC NC NC NC NC NC NC NC NC NC NC NC
45 44 43 39 38 37 21 10 11 12 5 4 3 * No connect pin
VDD
TEST 28 * Dedicated IC test pin. * Normally this pin is used connected to GND.
VDD
LTOUT RTOUT 33 16 * Equalizer output pins
VDD
LFIN RFIN 32 17 * Fader block input pins * Drive at low impedance.
Continued on next page. No. 7053-12/21
LC75412E, 75412W
Continued from preceding page.
Pin Name Pin No. Function Equivalent circuit
VDD
LFOUT LROUT RFOUT RROUT 31 30 18 19 * Fader output pins. Attenuation is possible separately for the front end and rear end. The attenuation amount is the same for L and R.
VDD
Vref
57
* Connect a capacitor of a few tens of F between Vref and AVSS (VSS) as a VDD/2 voltage generator, current ripple countermeasure.
LVref RVref
VDD
56
* Power supply pin
DVSS
27
* Logic system ground pin
LAVSS RAVSS
29 22
* Analog system ground pins
VDD
* External muting control pin MUTE 23 * Setting this pin to VSS level sets forcibly fader volume block to - level.
VDD
* Timer pin when there is no signal in the zero-cross circuit. TIM 20 Forcibly set data when there is no zero-cross signal, from the time the data is set until the timer ends.
CL DI
26 25
* Input pin for serial data and clock used for control
VDD
CE
24
* Chip enable pin. Data is written to the internal latch and the analog switches are operated when the level changes from High to Low. Data transfer is enabled when the level is High.
No. 7053-13/21
LC75412E, 75412W Internal Equivalent Circuit Block Diagram Selector Block Equivalent Circuit Block Diagram
R3=22.65k L5P R4=25k LVref L5M R1=22.65k
+ 0dB
+ 6.702k
LSELO
R2=25k
1.25dB 5.804k 2.50dB 5.026k 3.75dB
L6 50k LVref L4 50k LVref L3 50k LVref L2 50k LVref L1 50k LVref INMUTE SW LVref
4.352k 5.00dB 3.769k 6.25dB 3.264k 7.50dB 2.826k 8.75dB 2.447k 10.0dB 2.119k 11.25dB 1.835k 12.5dB 1.589k 13.75dB 1.376k 15.0dB 1.192k 16.25dB 1.032k 17.5dB 0.894k 18.75dB 5.774k LVref
Total resistance: 50 k Same for right channel Unit (Resistance: )
No. 7053-14/21
LC75412E, 75412W Volume Block Equivalent Circuit Block Diagram
LVRIN 0dB R1=5434 R2=4845 R3=4319 R4=3850 R5=3431 R6=3058 R7=2726 R8=2429 R9=2165 R10=1930 R11=1720 R12=1533 R13=1366 R14=1218 R15=1085 R16=967 R17=862 R18=768 R19=685 R20=610 R21=544 R22=485 R23=432 R24=385 R25=343 R26=306 R27=273 LCT 1M R86 1500 R81 1227 R82 1230 R83 1233 R84 1236 R85 -1dB -2dB -3dB -4dB -5dB -6dB -7dB -8dB -9dB -10dB -11dB -12dB -13dB -14dB -15dB -16dB -17dB -18dB -19dB -20dB -21dB -22dB -23dB -24dB -25dB -26dB -27dB R28=243 R29=216 R30=193 R31=172 R32=153 R33=839 R34=748 R35=667 R36=594 R37=530 R38=472 R39=421 R40=375 R41=334 R42=298 R43=266 R44=237 R45=211 R46=188 R47=168 R48=149 R49=133 R50=119 R51=106 R52=94 R53=84 R54=75 -28dB -29dB -30dB -31dB -32dB -33dB -34dB -35dB -36dB -37dB -38dB -39dB -40dB -41dB -42dB -43dB -44dB -45dB -46dB -47dB -48dB -49dB -50dB -51dB -52dB -53dB -54dB R55=133 R56=119 R57=106 R58=94 R59=84 R60=75 R61=134 R62=119 R63=106 R64=95 R65=84 R66=75 R67=134 R68=119 R69=106 R70=95 R71=85 R72=75 R73=134 R74=120 R75=107 R76=95 R77=85 R78=76 R79=67 R80=552 -55dB -56dB -57dB -58dB -59dB -60dB -61dB -62dB -63dB -64dB -65dB -66dB -67dB -68dB -69dB -70dB -71dB -72dB -73dB -74dB -75dB -76dB -77dB -78dB -79dB -
To tone block
Total resistance of 48.746 k over tap Total resistance of 1.256 k under tap (LOUD OFF) Total resistance of 7.662 k under tap (LOUD ON) Same for right channel Unit (Resistance: )
LVref
No. 7053-15/21
LC75412E, 75412W Tone Control Block Equivalent Circuit Diagram
+ -
+ -
+ -
LTOUT
SW2 SW1
SW3 SW1
SW2
SW3
0.655 18dB 2.189 16dB 2.756 14dB 3.470 12dB 4.368 10dB 5.498 8dB 6.923 6dB 8.715 4dB 10.972 2dB 13.813 0dB
SW4
0.655 18dB 2.189 16dB 2.756 14dB 3.470 12dB 4.368 10dB 5.498 8dB 6.923 6dB 8.715 4dB 10.972 2dB 13.813 0dB
SW4
3.90
3.90
LF1C1
LF1C2
LF1C3 LF3C1
LF3C2
LF3C3
Unit: k Total resistance: 59.359 k Same for right channel During boost, SW 1 and SW 3 are ON, during cut SW 2 and SW 4 are ON, and when 0 dB, 0 dB SW and SW 2 and SW 3 are ON.
No. 7053-16/21
LC75412E, 75412W F1/F3 Band Circuit The equivalent circuit and the formula for calculating the external RC with a mean frequency of 1 kHz are shown below. * F1/F3 band equivalent circuit block diagram
R1
R2
C1
C2
R3
* Calculation example Specification Mean frequency: f0 = 1 kHz Gain during maximum boost: G+18 dB = 18 dB Let us use R1 = 0.665 k, R2 = 58.704 k, and C1 = C2 = C.
G+18 dB = 20 x LOG10 1 +
R2 2R3+R1
1. Calculate R3 with G+18 dB = 18 dB:
R3 =
R2 10G/20 -1
- R1
/ 2 = 3900
2. Calculate C with the center frequency f0 = 1 kHz
f0= C=
1 2 (R1+R2)R3C1C2 = 0.010 x 10-6 0.01 F
1 1 = 2f0 (R1+R2)R3 2 x 1000 39359x3900
3. Calculate Q:
Q=
1 R3(R1+R2) 1.789 x (R1+R2)R3 (2R3+R1)
No. 7053-17/21
LC75412E, 75412W Fader Volume Block Equivalent Circuit Block Diagram
S1 LFIN 0dB 5.437k -1dB 4.846k -2dB 8.169k -4dB 6.489k -6dB 5.154k -8dB 4.094k -10dB 3.252k -12dB 2.583k -14dB 2.052k -16dB 1.630k -18dB 1.295k -20dB 3.419k -30dB 1.300k -45dB 0.231k -60dB 0.050k -dB Unit: Total resistance: 50 k Same for right channel When FADER = "1", S2 and S3 are ON. When FADER = "0", S1 and S4 are ON. S4 LROUT S3 S2 LFOUT
LVref When - data is sent to the main volume, S1 and S2 become open, and S3 and S4 simultaneously become ON.
No. 7053-18/21
LC75412E, 75412W Usage Cautions (1) Data transmission at power ON * The status of internal analog switches is unstable at power ON. Therefore, perform muting or some other countermeasure until the data has been set.
(2) Description of zero-cross switching circuit operation The LC75412E and 75412W have a function to switch zero-cross comparator signal detection locations, enabling the selection of the optimum detection location for blocks whose data is to be updated. Basically, the switching noise can be minimized by inputting the signal immediately following the block whose data is to be updated to the zero-cross comparator, so it is necessary to switch the detection location every time.
Selector
Volume
Tone
Fader
Switch Zero-cross comparator
LC75412E, 75412W Zero-Cross Detection Circuit (3) Zero-cross switching control method The zero-cross switching control method consists of setting the zero-cross control bits to the zero-cross detection mode (D36, D37 = 0), and specifying the detection blocks (D38, D39) before transmitting the data. These control bits are latched immediately following data transfer, that is to say beforehand in sync with the falling edge of CE, so when updating data of volumes, etc., it is possible to perform mode setting and zero-cross switching with one data transfer. An example of control when updating the data of the volume block is shown below.
D36 0 D37 0 D38 1 Volume block setting D39 0
Zero-cross detection mode setting
(4) Zero-cross timer setting If the input signal becomes lower than the zero-cross comparator detection sensitivity, or if only low-frequency signals are input, zero-cross detection continues to be impossible, and data is not latched during this time. The zero-cross timer can set a time for forcible latch during such a status when zero-cross detection is not possible. For example, to set 25 ms, using T = 0.69CR and C = 0.033 F, we obtain
R=
25 x 10 -3 0.69 x 0.033 x 10 -6
1.1 M
Normally, a value between 10 ms and 50 ms is set.
No. 7053-19/21
LC75412E, 75412W (5) Cautions related to serial data transfer 1. To ensure that the high-frequency digital signals transferred to the CL, DI, and CE pins do not spill over to the analog signal block, either guard these signal lines with a ground pattern, or perform transmission using shielded wires. 2. The data format of the LC75412E and 75412W uses 8-bit addresses and 44-bit data. When sending data using multiples of 8 (when sending 48 bits), use the method described in Figure 1. Method for Receiving Data Using Multiple of 8 of LC75412E and 75412W
X
X
X
X
D0
D1
D2
D3
D36
D37
D38
D39
D40
D41
D42
D43
Dummy data
Input switching control
Test mode control X : don't care
Figure 1 (6) Note on usage of external muting When using external mute function, take adequate countermeasures against noise to prevent malfunction.
20
Input Gain Step Characteristics
VDD = 9 V VIN = -20 dBV f = 1 kHz Overall
10
Output Level Characteristics
VDD = 9 V, VIN = 0, VR = 0 to -54 dB Overall
H 1k
z kH z
0
15
20
--10
Level -- dB
Level -- dB
--20
10
--30
5
--40
--50 0 0 2 4 6 8 10 12 14 16 18 20 --60 10
23
5 7 100
23
5 7 1k
23
5 7 10k
23
Step setting
10
ILC05454 0 --10 --20
Frequency, f -- Hz
57 100k ILC05455
Loudness Characteristics
VDD = 9 V, VIN = 0, VR = 0 to -54 dB Loudness ON, Overall
Feder Step Characteristics
VDD = 9 V VIN = 0 f = 1 kHz Overall
0
--10
--30
Level -- dB
Level -- dB
--20
--40 --50 --60 --70 --80
--30
--50 --90 --60 10 23 5 7 100 23 5 7 1k 23 5 7 10k 23 5 7100k ILC05456 --100 --
f=
--70 --60
1
kH
--40
f=
z
20
kH
z
--50
--40
--30
--20
--10
0
Frequency, f -- Hz
Step setting -- dB
ILC05457
No. 7053-20/21
LC75412E, 75412W F1 Band Characteristics
VDD = 9 V VIN = -20 dBV Overall
0 --5 --10
0 --5 --10
F3 Band Characteristics
VDD = 9 V VIN = -20 dBV Overall
Level -- dB
--20 --25 --30 --35 --40 10
Level -- dB
23 5 7 100 23 5 7 1k 23 5 7 10k 23 5 7100k ILC05458
--15
--15 --20 --25 --30 --35 --40 10
23
5 7 100
23
5 7 1k
23
5 7 10k
23
Frequency, f -- Hz
1.0 7 5 3 2 0.1 7 5 3 2 0.01 7 5 3 2 0.001 10 23 5 7 100 23
Frequency, f -- Hz
1.0 7 5 3 2 0.1 7 5 3 2 0.01 7 5 3 2 0.001 --40 --35 --30 --25 --20 --15 --10 --5
5 7100k ILC05459
THD -- Frequency Characteristics
Total harmonic distortion, THD -- % VDD = 9 V 80 kHz LPF Overall
THD -- Input Level Characteristics
VDD = 9 V 80 kHz LPF Overall
Total harmonic distortion, THD -- %
VIN = 0 dBV
VIN = -10 dBV
5 7 1k 23 5 7 10k 23 5 7100k ILC05460
z kH 20 z kH 10 Hz 1k
0
5
Frequency, f -- Hz
Input level -- dBV
ILC05461
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of Octomber, 2001. Specifications and information herein are subject to change without notice. PS No. 7053-21/21

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